There is a problem that as integrated circuits becomes finer (scaling) and the integrated circuits have a higher capacity, the off-state leakage current of a transistor such as a MOSFET which is a basic element of the integrated circuits, e.g. SRAM (FIG. 27), increases, resulting in increased power consumption therein.
Therefore, an attempt to power off an integrated circuit has been made to reduce an off-leak when information processing is not carried out in the integrated circuit. For example, there is a method in which data stored in a volatile storage circuit and/or the like included in an integrated circuit is saved into a storage element with a long data retention time prior to power off, and the data saved into the storage element with a long data retention time is restored in the volatile storage circuit and/or the like after power on to return a circuit state to a state prior to the power off.
Magnetic tunnel junction (MTJ) elements, a resistance-change-type memory (ReRAM), a phase-change memory (PCRAM), or the like have been considered to be adopted as a nonvolatile storage element for retaining data during the power-off period described above.
Examples in which such MTJ elements as mentioned above are used as nonvolatile storage elements are as follows.
FIG. 28 is a circuit diagram of a nonvolatile storage circuit 110 reported in Non Patent Literature 1. The nonvolatile storage circuit 110 comprises: a volatile SRAM 102 comprising six transistors; and two spin-injection-type MTJ elements 113 and 114 connected to the storage nodes C and D of the SRAM 102.
In the nonvolatile storage circuit 110, data is written in the SRAM 102 in a normal writing operation. Further, data is written in the MTJ elements 113 and 114 just before power-off. Since the MTJ elements 113 and 114 are nonvolatile, power supply to the nonvolatile storage circuit 110 can be stopped to allow a stand-by power to be zero in a stand-by state.
FIG. 30 is a circuit diagram of another nonvolatile storage circuit 115 disclosed in Non Patent Literature 1. The nonvolatile storage element 115 comprises n-type MOSFETs 116 and 117 as well as the SRAM102 and spin-injection-type MTJ elements 113 and 114 as in the nonvolatile storage element 110 illustrated in FIG. 28. The n-type MOSFETs 116 and 117 are placed between the SRAM 102 and the MTJ elements 113 and 114.
In the nonvolatile storage circuit 115, the n-type MOSFETs 116 and 117 are turned off to separate the MTJ elements 113 and 114 from the SRAM 102 during writing and reading. Accordingly, writing and reading operations are carried out for the volatile SRAM 102 comprising the six transistors. Just before a stand-by state is achieved, the n-type MOSFETs 116 and 117 are turned on to write data stored in the SRAM102 into the MTJ elements 113 and 114, and then, power supply to the nonvolatile storage circuit 115 is stopped. In such a manner, a stand-by power is allowed to be zero.
FIG. 31 is a circuit diagram of a nonvolatile storage circuit 120 disclosed in Non Patent Literature 2. The nonvolatile storage circuit 120 comprises 32 memory cells 122. Each memory cell 122 comprises four transistors 125 and two spin-injection-type MTJ elements 113 and 114. The 32 memory cells 122 are connected to a PL driver via power lines PL. The PL driver carries out power gating for controlling power supply to the 32 memory cells via the power lines PL.
In an access state, the PL driver carries out the control so that of the 32 memory cells 122 power is supplied only to a memory cell 122 for writing. Thus, data is written in the MTJ elements 113 and 114 of the memory cell 122 for writing. In a stand-by state, the PL driver allows all the power lines PL to be at low levels. Thus, the stand-by power of the nonvolatile storage circuit 120 can be allowed to be zero. In addition, the number of the memory cells 122 to be controlled by the PL driver are a few (in this case, 32), and therefore, processing in switching between the stand-by state and the access state is less time-consuming.
Non Patent Literature 3 describes an SRAM (8TSRAM) which comprises eight transistors and in which a path for exclusive use in reading is disposed to separate the reading path and a writing path from each other.